This invention relates to signal processing, and more particularly to a multiplexing circuit for phase locked loop applications.
Phase locked loops are used for a variety of communication applications. Some phase locked loop circuits employ a multiplexer for configuring the loop to different modes of operation. Conventional multiplexing arrangements have limited options in configuring the loop for different applications. On the other hand, using multiple loops can cause power penalty, and may consume too much area in a semiconductor chip. Further, there may be performance degradation associated with using more than one loop, if not properly implemented.
These and other problems with conventional multiplexing arrangements therefore create a need for a high-performance, low-jitter configurable multiplexing circuit.